The present invention relates to a method and/or architecture for controlling a device without a JTAG port and, more particularly, to an architecture and logic to control a device without a JTAG port through a device with a JTAG port.
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-product(SOP) terms in response to the product terms, and a number of logic elements (i.e., macrocells) configured to generate a desired output in response to the sum-of-products terms. The sum-of-products terms can also be generated using programmable NOR-NOR logic.
The arrangement and operation of components within the PLD are programmed by architecture configuration bits. The architecture configuration bits are set prior to normal operation of a PLD. The configuration bits can be stored in volatile memory (i.e., SRAM) or non-volatile memory (i.e., EEPROM/flash). The bits are set using an operation called xe2x80x9cprogrammingxe2x80x9d or xe2x80x9cconfigurationxe2x80x9d. When the configuration bits are stored in volatile memory, the configuration bits need to be loaded from an off-chip non-volatile memory, a micro controller, or some other source. When an off-chip non-volatile memory is used, the memory can be pre-programmed to contain the necessary configuration data.
A PLD can also be programmed using a JTAG port as specified in the IEEE std 1149.1-1990 specification. The JTAG port can be used to program and test the PLD. However, the off-chip non-volatile (NV) memory devices do not have JTAG ports. In order to reprogram a memory packaged with a PLD, the package would need to have extra pins for the required programming signals. If the PLD and memory are separate chips on a circuit board, the circuit board would need to provide the extra space for the necessary programming circuitry.
A solution that would allow control of a device without JTAG support from a device with JTAG support would be desirable.
The present invention concerns an apparatus comprising a first circuit comprising a JTAG port and a second port. A JTAG non-compliant circuit may be controlled by the JTAG port when connected to the second port.
The objects, features and advantages of the present invention include providing an architecture and logic that may (i) control a device without a JTAG port through a device that has a JTAG port, (ii) control the operation of any off chip device, (iii) control an off chip flash memory, (iv) allow control of pulse widths of control signals for an off-chip device using run test idle state of the TAP controller, and/or (v) implement a JTAG compliant NV memory device out of a traditional off-the-shelf NV core that has no JTAG interface.